1. Technical Field
The present invention relates to a signal output circuit provided with an emitter follower.
2. Related Art
Most semiconductor-based circuits include an emitter follower that serves as a buffer or the like. The emitter follower generally includes a transistor and a constant current source provided on the emitter side of the transistor, so as to provide a constant current irrespective of whether a signal is input.
When the emitter follower is employed in a signal output circuit, a load such as a load resistance or a load capacitor is connected to the output. Such load reduces the operating speed of the emitter follower.
Accordingly, for example Japanese Laid-open utility model publication No.H05-70020 proposes employing a comparator to restrain the reduction in operating speed of the emitter follower. The circuit according to the publication includes a comparator to which an output voltage of the emitter follower and a reference voltage are input, so that the output of the comparator is connected to the constant current source of the emitter follower. A signal generated by the comparator representing a variation in output voltage of the emitter follower increases a current of the constant current source of the emitter follower. This serves to increase the operating speed of the emitter follower.
The signal output circuit according to the publication includes NPN-type transistors 101, 102, and a comparator 103, as shown in FIG. 6. The base of the transistor 101 is connected to an input signal terminal 104, the emitter thereof to a constant current source 105 and a load capacitor 106, and the collector thereof to a terminal of a load 107. The other terminal of the load 107 is connected to a high-voltage side power source (not shown).
The transistor 102, the base of which is connected to an output terminal of the comparator 103, is connected in parallel with the constant current source 105. The transistor 102 is turned on and off according to the output signal of the comparator 103. The comparator 103 compares a collector potential of the transistor 101 and a potential at the node between a load 108 and a constant current source 109 connected to a terminal of the load 108, and outputs the comparison result. Specifically, the collector potential of the transistor 101 is provided to a non-inverted input terminal of the comparator 103, and the potential at the above node is provided to the inverted input terminal. The other terminal of the load 108 is connected to the high-voltage side power source. The output of such signal output circuit appears at an output terminal 110 provided between the emitter of the transistor 101 and the load capacitor 106.
The signal output circuit shown in FIG. 6 operates as follows. When the base of the transistor 101 receives an input, in other words a high signal (H) is input thereto, the emitter potential of the transistor 101 varies in conformity therewith. During such variation of the emitter potential, the collector current of the transistor 101 increases, so that the collector potential of the transistor 101 decreases by a voltage obtained upon multiplying the current that has increased by the resistance value of the load 107. Also, the current that has increased flows to the load capacitor 106, thus to be charged therein. On the other hand, the potential at the node between the load 108 and the constant current source 109 remains constant irrespective of whether the signal has been input. At this stage, a difference in potential corresponding to the voltage generated by the foregoing current variation is created between the input terminals of the comparator 103, which, though, does not activate the comparator 103 yet.
Then the input signal falls to a low level (L) after being maintained at a high level for a certain period. This causes the emitter potential of the transistor 101 to drop to the low level from the high level. During such variation, the transistor 101 is temporarily turned off. At this moment the voltage fall that has been so far taking place at the load 107 ceases, thereby causing the collector voltage of the transistor 101 to increase. Since the collector voltage of the transistor 101 is input to one of the input terminals of the comparator 103, while the other input terminal of the comparator 103 receives a constant current as stated earlier, a difference in potential is created between the input terminals of the comparator 103.
At this stage, the potential provided to the non-inverted input terminal of the comparator 103 becomes higher than the potential provided to the inverted input terminal. Accordingly, the comparator 103 is turned on and outputs a high level. This turns on the transistor 102, which is connected to the output of the comparator 103, so as to cause the load capacitor 106 to discharge a current. The circuit shown in FIG. 6 thus prevents the reduction in operating speed caused by the discharge current of the load capacitor, during the falling edge of the input signal.